Cadence Design Systems, Inc.
System and method for electrically and spatially aware parasitic extraction

Abstract:

The present disclosure relates to a computer-implemented method for parasitic extraction. The method may include providing, using one or more processors, an electronic design having IP and/or metal fill content associated therewith. The method may further include identifying at least one layer associated with the content to be modeled and identifying at least one layer associated with the content to be ignored. The method may also include discarding one or more shapes associated with the at least one layer associated with the content to be modeled and replacing each discarded shape with an alternative shape. The method may further include modeling the electronic design including the alternative shape, wherein modeling is electrically aware in a horizontal and a vertical direction. The method may further include a spatial modeling approach where non-extractable shapes are exclusively grouped across the design area including multiple layers, keeping configurable spatial separation between neighboring extractable shapes.