Cadence Design Systems, Inc.
Systems and methods for routing a clock net with multiple layer ranges

Abstract:

Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.