Cadence Design Systems, Inc.
Method and system for processing verification tests for testing a design under test

Abstract:

A method for processing verification tests for testing a design under test (DUT), may include receiving from a user a start time message and an end time message for each action of actions in a verification test in a target code form, to be printed into a log file of an execution of the test, so as to list chronologically the start time and end time of each of the actions in the log file. The method may also include executing the verification test to obtain the log file with the start time and end time messages and, using a processor, analyzing the log file to construct a graph representation of the validation test, based on the printed start and end times of the actions of the test.