Cadence Design Systems, Inc.
Interface modeling for power analysis of an integrated circuit

Abstract:

The present embodiments relate to generation of an interface model for performing a power analysis on a hierarchical integrated circuit design. According to some aspects, embodiments relate to a method of power analysis. The method can include partitioning an integrated circuit design into at least a first partition and a second partition sharing an interface with the first partition. The method can include generating a connectivity database of a signal net traversing from the first partition to the second partition across the first interface. The method can include determining a slew rate and a signal arrival time at the input pin of the destination cell, a capacitance load of the signal net, and one or more signal transitions and signal states on the signal net. The method can include calculating the power consumption of the circuit elements in the first partition using the connectivity database, and the determined information.