Cadence Design Systems, Inc.
Layout placement mapping from schematic placement of circuit cells

Abstract:

The present embodiments relate to implementing an integrated circuit design where a layout of circuit cells on a semiconductor chip is based on positions of the circuit cells on a schematic. According to some aspects, embodiments relate to a method for identifying a plurality of sub-regions on a semiconductor chip layout where each sub-region has a placement constraint. The method further includes assigning circuit cells to sub-regions based on the constraints. The method also includes clustering the circuit cells into clusters based on their positions on the schematic. Circuit cells from each cluster are placed in one or more of the sub-regions based on the proximity of the centers of the clusters to the centers of the sub-regions.