Cadence Design Systems, Inc.
Reduced resource harmonic balance circuit simulations

Abstract:

A system, method, and computer program product for reduced resource harmonic balance circuit simulations is disclosed, wherein a lattice structure is implemented in place of conventional approaches in order to reduce the amount of data being processed in each iteration of the harmonic balance process. Additionally, sparse frequency cuts, which correspond to the lattice structures, are disclosed. The sparse frequency cuts and the lattice structure may be may be customized, modified, and/or adjusted to match a variety of circuits with non-linear components, such as those found in microwave, RF, and multicarrier (e.g. LTE) implementations.