Ciena Corporation
Apparatus and methods for low power clock generation in multi-channel high speed devices

Abstract:

Described are apparatus and methods for low power clock generation in multi-channel high speed devices. In implementations, a multi-channel data processing device includes a low frequency clock generation and distribution circuit configured to generate and distribute a 1/N sampling frequency (F.sub.S)(F.sub.S/N) clock, wherein N is larger or equal to 8, and multiple data processing channels connected to the low frequency generation and distribution circuit. Each data processing channel including input ports associated with different operating frequency clocks, and a channel local clock generation circuit comprising multipliers associated with some of the input ports, each multiplier configured to multiply the F.sub.S/N frequency clock to locally generate an operating frequency clock associated with an input port of the input ports.