Ciena Corporation
Increasing random access bandwidth of a DDR memory in a counter application

Last updated:

Abstract:

Systems and methods include storing one or more counters in a plurality of locations in Double Data Rate (DDR) Random Access Memory (RAM) such that each counter is stored partially in multiple locations across the DDR RAM; and accessing banks in the DDR RAM sequentially for read operations and write operations associated with the one or more counters. The multiple locations include a location in each bank of the banks in the DDR RAM. A read operation for a counter is performed by reading all of the corresponding multiple locations and combining associated values to return a result for the counter. A write operation for a counter is performed by writing to a location of the multiple locations that is currently in sequence.

Status:
Application
Type:

Utility

Filling date:

13 Nov 2020

Issue date:

19 May 2022