Ciena Corporation
COMPANION AND HOST CHIP PHOTONIC INTEGRATION

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Abstract:

At least a portion of an integrated circuit wafer includes at least one layer in which two or more waveguides are formed. A cavity is formed in the integrated circuit wafer. At least one die, comprising a photonic integrated circuit, has: at least one edge on which there are two or more optical mode defining structures in proximity to respective optical mode defining structures on at least one surface of the cavity, a bottom surface secured to a bottom surface of the cavity, and a top surface on which there is at least one metal contact.

Status:
Application
Type:

Utility

Filling date:

15 Dec 2020

Issue date:

16 Jun 2022