Ciena Corporation
Fractional frequency synthesis by sigma-delta modulating frequency of a reference clock

Abstract:

A circuit includes a programmable frequency divider which receives a high-speed clock, f.sub.in, as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.