Cisco Systems, Inc.
Sense amplifier flip-flop

Abstract:

A flip-flop is provided that includes an input latch, configured to receive a data signal and a complement and produce set and reset pulses based on a clock and a difference between the data signal and the complement; and an output latch, configured to store a data value in a first memory and a complement data value in a second memory based on the set and reset pulses and the clock. Various buffers configured to invert and amplify the set and reset pulses before provision to the output latch stages are optionally disposed between the input and output latches. The input latch includes two signal arms, two difference transistors (one gate controlled by the clock and the other by a clock complement) coupled oppositely to one another (by respective drains and sources) to the signal arms, and two regeneration inverters coupled oppositely to one another to the signal arms.