Cisco Systems, Inc.
Implementing configurable packet parsers for field-programmable gate arrays using hardened resources

Abstract:

Techniques for improving the ability of FPGAs to process packets by implementing at least portions of the logic of packet parsers traditionally performed using the FPGA fabric as hardened resources, such as an Integrated Circuit (IC) block. The IC block receives bits of an incoming packet, carries these bits as a pipeline, and modifies a range of the bits through stages of aligners. The aligners extract header sections (or "windows") of each packet header according to a shift amount, and the header sections are output to the FPGA fabric. The FPGA fabric includes extract and decision logic that maps the information included in the extracted header sections to a lookup vector, driving tables, and/or application logic. The FPGA provides shift amounts to subsequent aligners to cause the aligners to shift the packet bus such that previous header sections are removed.