Entegris, Inc.
3-DIMENSIONAL NAND MEMORY WITH REDUCED THERMAL BUDGET

Abstract:

Methods of manufacture and memory cells manufactured according to the methods are described. The manufacture has a lower thermal budget and experiences less heating by including a blocking layer including MgO. The method of manufacture may include annealing following deposition of the MgO, with the annealing occurring at temperatures below 900.degree. C. or below 800.degree. C. The blocking layers may be a first blocking layer made of SiO.sub.2 and a second blocking layer made of MgO. The memory cells may have a CMOS Under Array (CuA) structure. The memory cells may be part of a three-dimensional NAND memory device.