Honeywell International Inc.
Source-coupled logic with reference controlled inputs

Abstract:

A source-coupled logic (SCL) gate configured to reduce power supply noise generation and reduce DC power consumption by adjusting a bias current to deliver only the performance level required for a given application. The SCL gate circuit arrangement includes a current mirror circuit with transistors configured as pull-up transistors. The pull-up transistors set the logical HIGH voltage level. The SCL gate circuit may also include voltage limiting devices configured to set the logical LOW voltage level. The current mirror circuit and the voltage limiting devices allow the SCL gate to receive a bias current supplied a bias circuit that is less complex than bias circuitry used by other examples of SCL circuitry. Adjusting the bias current delivers the desired performance with the commensurate reduction in power consumption.