Honeywell International Inc.
Efficient ingress-congruency determination in a network

Abstract:

In an embodiment, a computing node includes a computing circuit, a comparing circuit, and an indicator circuit. The computing circuit is configured to receive each of at least one input-data message. The comparing circuit is configured to compare each of the at least one received input-data message to a list of input-data-message identifiers. And the indicator circuit is configured, for each of the at least one input-data message that corresponds to a respective input-data-message identifier, to generate a respective portion of a first status message, the respective portion indicating that the input-data message was received. For example, such computing node can determine the congruency of a received input-data message between coupled redundancy circuits with reduced processing overhead, reduced message delay, and reduced message latency as compared to existing computer nodes.