International Business Machines Corporation
Structure and method to fabricate fully aligned via with reduced contact resistance

Abstract:

Techniques are provided to fabricate semiconductor devices. For example, a method includes forming a lower level interconnect line having a first hardmask layer thereon and embedded in a lower level dielectric layer. The first hardmask layer is removed to form a first opening having a first width in the lower level dielectric layer. The sidewalls of the lower level dielectric layer are etched in the first openings to form a second opening having a second width. The second width is greater than the first width. An upper level interconnect line is formed on the lower level interconnect line.