International Business Machines Corporation
Synchronizing access to shared memory by extending protection for a target address of a store-conditional request

Abstract:

A processing unit includes a processor core that executes a store-conditional instruction that generates a store-conditional request specifying a store target address. The processing unit further includes a reservation register that records shared memory addresses for which the processor core has obtained reservations and a cache that services the store-conditional request by conditionally updating the shared memory with the store data based on the reservation register indicating a reservation for the store target address. The cache includes a blocking state machine configured to protect the store target address against access by any conflicting memory access request snooped on a system interconnect during a protection window extension following servicing of the store-conditional request. The cache is configured to vary a duration of the protection window extension for different snooped memory access requests based on one of broadcast scopes and the relative locations of masters of the snooped memory access requests.