International Business Machines Corporation
CMOS-compatible high-speed and low-power random number generator

Abstract:

CMOS-compatible high-speed and low power random number generator and techniques for use thereof are provided. In one aspect, a random number generator includes: a noise amplification unit configured to generate an amplified noise signal, wherein the noise amplification unit includes noise amplification unit transistors having a threshold voltage (V.sub.t,amp) of about 0; and a computing unit configured to process the amplified noise signal from the noise amplification unit to generate a stream of random numbers, wherein the computing unit comprises computing unit transistors having absolute values of a V.sub.t,compute that are larger than the V.sub.t,amp of the noise amplification unit transistors in the noise amplification unit. For digital implementations, an analog-to-digital converter configured to digitize the amplified noise signal can be employed. For analog implementations, a sample and hold circuit configured to sample the amplified noise signal can be employed. A method for random number generation is also provided.