International Business Machines Corporation
FLOORPLAN OF A DESIGN FOR AN INTEGRATED CIRCUIT

Abstract:

A computer-implemented method for comparing a first version of a floorplan of a design for an integrated circuit with a second version. The method comprises (i) generating a timing information for each net in the second version by determining whether timing information is available for the net in the first version; (ii) in case no timing information is available in the first version, generating the timing information for the second version by calculating a spatial distance and timing information between two points of the net using wire length differences between the first version and the second version; (iii) otherwise, generating the timing information for the second version by calculating a spatial distance and timing information between two points of the net using a wire reach table to obtain a wire delay.