International Business Machines Corporation
REDUCTION OF BOTTOM EPITAXY PARASITICS FOR VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

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Abstract:

A semiconductor device structure comprises at least one semiconductor fin for a vertical transport field effect transistor, a bottom source/drain layer, and an insulating layer underlying the bottom source/drain layer. A method of forming the structure comprises forming a sacrificial layer within a lower portion of a source/drain region for a vertical transport field effect transistor structure. The sacrificial layer being formed adjacent to at least one semiconductor fin and in contact with a substrate. A source/drain layer is formed within an upper portion of the source/drain region above the sacrificial layer. The sacrificial layer is removed thereby forming a cavity between the substrate and the source/drain layer. An insulating layer is formed within the cavity.

Status:
Application
Type:

Utility

Filling date:

24 Mar 2020

Issue date:

30 Sep 2021