International Business Machines Corporation
Speculative address translation requests pertaining to instruction cache misses

Abstract:

A central processing unit (CPU) sets a cache lookup operation to a first mode in which the CPU searches a cache and only performs an address translation in response to a cache miss. The CPU performs the cache lookup operation while in the first mode using an address that results in a cache miss. Responsive to the CPU detecting the cache miss, the CPU sets the cache lookup operation from the first mode to a second mode in which the CPU concurrently searches the cache and performs an address translation. The CPU performs a cache lookup operation while in the second mode using a second address that results in a cache hit. Responsive to detecting the cache hit, the CPU sets the cache lookup operation from the second mode to the first mode. This process repeats in cycles upon detection of cache hits and misses.