International Business Machines Corporation
Barrier-free vertical interconnect structure

Abstract:

A semiconductor device includes a first interconnect structure formed in an M.sub.X level of the semiconductor device, the M.sub.X level includes a third interlevel dielectric layer located above a second capping layer, a first trench within the third interlevel dielectric layer extending through the second capping layer to expose a top surface of a contact structure located below the second capping layer, the contact structure is located within a second interlevel dielectric layer, a second metal liner conformally deposited within the first trench, and a first seed layer conformally deposited above the second metal liner, the first seed layer includes a metal manganese film. A first thermal annealing process is conducted on the semiconductor device to form a first barrier liner underneath the second metal liner to prevent diffusion of conductive metals.