International Business Machines Corporation
INITIATING INTERCONNECT OPERATION WITHOUT WAITING ON LOWER LEVEL CACHE DIRECTORY LOOKUP

Abstract:

An upper level cache receives from an associated processor core a plurality of memory access requests including at least first and second memory access requests of differing first and second classes. Based on class histories associated with the first and second classes of memory access requests, the upper level cache initiates, on the system interconnect fabric, a first interconnect transaction corresponding to the first memory access request without first issuing the first memory access request to the lower level cache via a private communication channel between the upper level cache and the lower level cache. The upper level cache initiates, on the system interconnect fabric, a second interconnect transaction corresponding to the second memory access request only after first issuing the second memory access request to the lower level cache via the private communication channel between the upper level cache and the lower level cache and receiving a response to the second memory access request from the lower level cache.