International Business Machines Corporation
Vertical field effect transistor with reduced parasitic capacitance

Abstract:

A vertical field effect transistor (VFET) has a top source/drain (S/D) with a first region having a first area and a first capacitance and a second region having a second area and a second capacitance. A first top spacer on a gate cross section area. A second top spacer with a varying thickness is disposed the first top spacer. Both the first and second top spacers are between the top S/D and the gate cross section area. Due to the varying thickness of the second spacer with the smaller thickness closer to the fin, the separation distance between the larger, first area and the gate cross section area is greater than the separation distance between the smaller, second area and the gate cross section area. Therefore, the first capacitance is reduced because of the larger separation distance and the second capacitance is reduced because of the smaller second area. The smaller thickness of the second top spacer being closer to the fin allows dopants to diffuse a shorter distance when forming a junction between the top S/D and the channel of the VFET.