International Business Machines Corporation
Real-time eye diagram optimization in a high speed IO receiver

Abstract:

A example receiver includes analog circuitry configured to equalize and amplify an input signal and provide an analog signal as output; clock data recovery (CDR) circuitry configured to recover data clocks and edge clocks from the analog signal; a plurality of eye height optimization circuits, each of the plurality of eye height optimization circuits configured to, based on a respective data pattern of a plurality of data patterns, sample the analog signal based on the data clocks and the edge clocks, feed back first information to the analog circuitry for adjusting the eye amplitude, and feed back second information to the CDR circuitry for adjusting the data clocks; and an eye width optimization circuit configured to receive data and edge samples from the plurality of eye height optimization circuits, feed back third information to the CDR circuitry to adjust the edge clocks, and feed back fourth information to the analog circuitry to adjust the equalization.