International Business Machines Corporation
Path-based timing driven placement using iterative pseudo netlist changes

Abstract:

Carry out an initial wire-length-driven placement for an integrated circuit design embodied in an unplaced netlist, using a computerized placer, to obtain a data structure representing initial placements of logic gates. Identify at least one timing-critical source-sink path between at least one pair of source-sink endpoints in the data structure representing the initial placements. Create a new pseudo two-pin net for each pair of the at least one pair of source-sink endpoints to create an updated netlist. Carry out a revised wire-length-driven placement on the updated netlist to obtain a data structure representing revised placements.