International Business Machines Corporation
MEMORY-MAPPED NEURAL NETWORK ACCELERATOR FOR DEPLOYABLE INFERENCE SYSTEMS

Abstract:

A neural network processor system is provided comprising at least one neural network processing core, an activation memory, an instruction memory, and at least one control register, the neural network processing core adapted to implement neural network computation, control and communication primitives. A memory map is included which comprises regions corresponding to each of the activation memory, instruction memory, and at least one control register. Additionally, an interface operatively connected to the neural network processor system is included, with the interface being adapted to communicate with a host and to expose the memory map.