International Business Machines Corporation
Self-aligned top via scheme

Last updated:

Abstract:

A semiconductor device includes a base structure including a lower level via and a lower level dielectric layer, a conductive pillar including an upper level line and an upper level via disposed on the lower level via, and a protective structure disposed between the lower level via and the upper level line. The protective structure includes a material having an etch rate less than or equal to that of the lower level via.

Status:
Grant
Type:

Utility

Filling date:

14 Aug 2019

Issue date:

3 May 2022