International Business Machines Corporation
IN-MEMORY RESISTIVE RANDOM ACCESS MEMORY XOR LOGIC USING COMPLIMENTARY SWITCHING

Abstract:

In a method for using or forming a semiconductor structure. The semiconductor structure may include a resistive random access memory (RRAM) gate with a first electrode and a second electrode. The RRAM gate may also include a switching layer that includes a dielectric material having a switching layer k-value and a switching layer thermal conductivity. The RRAM gate may also include a complimentary switching (CS) mitigation layer with a material having a CS k-value that is lower than the switching layer k-value and a CS thermal conductivity that is higher than the switching layer thermal conductivity.