International Business Machines Corporation
Frequency divider with delay compensation

Abstract:

A method and apparatus for controlling a frequency range of a self-resonant frequency (SRF) of a high speed divider implemented in current mode logic (CML) D triggers by controlling a field effect transistor (FET) load resistor bias voltage to FETs operating in linear regions in load resistors in the CML D triggers. Tail currents of the CML D triggers are controlled to track inversely to a resistor value.