International Business Machines Corporation
Multi-cycle latch tree synthesis

Abstract:

For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.