Infinera Corporation
CLOCK RECOVERY FOR POINT-TO-MULTI-POINT COMMUNICATION SYSTEMS

Abstract:

Consistent with the present disclosure independent phase and frequency clock recovery on each SC. Both leaf and hub perform digital clock recovery on each SC by increasing the Rx-ADC sampling rate by a few ppm (.about.16 ppm), and using a delay compensating element, together with gapped clocks. The gaps and delay compensating elements are independent on each SC. The delay element is performed using the frequency domain DSP engine, where the frequency domain equalizer coefficients are modified with a delay compensating element Thus, each SC can have its own fine timing frequency and timing phase tuning, and fine tracking of its own jitter. When the delay compensating element, which, for example, may include a finite impulse response (FIR) filter, reaches the end of its range, a clock gap equal to an integer number of symbols is performed. The delay element can be reset by the same number of symbols providing continuous phase interpolation.