Intel Corporation
Systolic similarity estimation with two-dimensional sliding window

Abstract:

A systolic array implemented in circuitry of an integrated circuit, includes a processing element array having processing elements arranged in a vertical direction and a horizontal direction, first loaders communicatively coupled to the processing element array to load samples A.sub.m,n from at least one external memory to the processing element array, and second loaders communicatively coupled to the processing element array to load samples B.sub.k,l from the at least one external memory to the processing element array. Each row of the samples A.sub.m,n is loaded one row at a time to a single processing element along the horizontal direction, and each row of the samples B.sub.k,l is loaded one row at a time to a single processing element along the vertical direction, wherein pairing between the samples A.sub.m,n and B.sub.k,l in the horizontal direction and the vertical direction enables data reuse to reduce bandwidth usage of the external memory.