Intel Corporation
High performance interconnect physical layer

Abstract:

A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.