Intel Corporation
Bridge die design for high bandwidth memory interface

Abstract:

A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another.