Intel Corporation
Measuring per-node bandwidth within non-uniform memory access (NUMA) systems

Abstract:

A computing system includes a plurality of nodes including a first node, the first node including at least one core, a memory controller, a node-track register (MSR), and a monitoring counter array including a plurality of counters. The memory controller is to access a plurality of bits of the node-track MSR to determine a subset of nodes to be tracked, wherein the subset of nodes includes the first node and a second node. The memory controller is further to allocate a first counter of the plurality of counters to track memory requests sent to a local system memory by the first node; and allocate a second counter of the plurality of counters to track a memory response associated with a memory request sent by the first node to the second node.