Intel Corporation
Receiver circuitry for physical coding sublayer

Abstract:

Circuitry and methods for receiving data that may be compliant with a specific protocol is discussed. The described systems may be employed to implement a physical media access (PMA) sublayer and/or physical coding sublayer (PCS) for high-speed Ethernet protocols. Embodiments described herein may have reduced circuitry footprint that may be achieved by the use of a single recovered clock to drive the operations of PCS circuitry. Efficient use of components may also be achieved by the use of smaller-sized words for processing by the PCS circuitry. The circuitry may process the smaller-sized words by implementing pipelined circuitry. Implementations that employ programmable circuitry, hardened circuitry, or hybrid implementations are also discussed.