Intel Corporation
RESISTANCE REDUCTION FOR WORD LINES IN MEMORY ARRAYS

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Abstract:

Apparatus, systems, or methods for a memory array having a plurality of word lines. A word line includes at least one word line plate, and the word line plate comprises a first material with a first resistivity. An edge of the word line plate is recessed and filled with a second material having a second resistivity that is lower than the first resistivity. As a result, the total resistance of the word line may be reduced compared to a word line using only the first material with the first resistivity. Other embodiments may also be described and claimed.

Status:
Application
Type:

Utility

Filling date:

24 Feb 2020

Issue date:

26 Aug 2021