Intel Corporation
SRAM with hierarchical bit lines in monolithic 3D integrated chips

Abstract:

A memory device includes a first plurality of memory cells, a second plurality of memory cells, and a local sense amplifier between the first plurality of memory cells and the second plurality of memory cells, all on a first level, and a local bit line on a second level. The second level is vertically separated by one or more first inter-level dielectric layers from the first level in a first direction and the local bit line is electrically coupled to each memory cell of the first plurality of memory cells and the second plurality of memory cells, as well as the local sense amplifier. The memory device also includes a global bit line on a third level vertically separated by one or more inter-level dielectric layers from the first level in a second direction opposite the first direction, with the global bit line electrically coupled to the local sense amplifier.