Intel Corporation
FPGA Processing Block for Machine Learning or Digital Signal Processing Operations

Abstract:

The present disclosure describes a digital signal processing (DSP) block that includes a columns of weight registers that can receive values and inputs that can receive multiple first values and multiple second values, where the multiple first values may be stored in the weight registers after being received at the inputs. Additionally, the DSP block includes multipliers that, in a first mode of operation, simultaneously multiply each of the first values by a value of the multiple second values. The DSP block, in a second mode of operation, enables a first column of multipliers of the multipliers to multiply each of multiple third values by each of multiple fourth values, where at least one of the multiple third values or fourth values includes more bits than the first values and second values.