Intel Corporation
Bypassing cache memory in a write transaction in a system with multi-level memory

Abstract:

Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.