Intel Corporation
Efficient rotate adder for implementing cryptographic basic operations

Abstract:

Integrated circuits to compute a result of summing m values, rotating the sum by k bits, and adding a summation of n values B.sub.i to B.sub.n to the rotated sum. An embodiment includes: a first carry save adder to add up the m values to generate a first carry and a first sum; rotator circuitry to rotate both the first carry and the first sum by k bits to generate a second carry and a second sum; a second carry save adder to add up the second carry, the second sum, and the summation of values B.sub.i to B.sub.n to generate a third carry and a third sum; two parallel adders to generate a first intermediate result and a second intermediary result based on the third carry and the third sum; and a multiplexer to generate the result utilizing various portions of the first and second intermediate results.