Intel Corporation
LOW POWER APPARATUS AND METHOD TO MULTIPLY FREQUENCY OF A CLOCK

Abstract:

A multi-feedback circuit that compares a duty cycle corrected reference clock f.sub.REF, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32.times., 4.times., etc.) of the frequency of f.sub.REF with approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.