Intel Corporation
JTAG scans through packetization

Last updated:

Abstract:

A Joint Test Access Group (JTAG) device can include a Joint Test Access Group (JTAG) port, transport layer circuitry to provide a communication to and from a debug device, and packet interpreter circuitry communicatively coupled between the JTAG port and the transport layer circuitry, the packet interpreter circuitry to translate data in a packet from the debug device into a sequence of bits to be provided to the JTAG port.

Status:
Grant
Type:

Utility

Filling date:

11 Dec 2017

Issue date:

14 Dec 2021