Intel Corporation
Apparatus and method for multiplication and accumulation of complex values

Abstract:

An apparatus and method for multiplying packed signed words. For example, one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed signed words; a second source register to store a second plurality of packed signed words; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to multiply each of a plurality of packed signed words from the first source register with corresponding packed signed words from the second source register to generate a plurality of products responsive to the decoded instruction, adder circuitry to add the products to generate a first result, and accumulation circuitry to combine the first result with an accumulated result to generate a final result comprising a third plurality of packed signed words, and to write the third plurality of packed signed words or a maximum value to a destination register.