Intel Corporation
SOC ARCHITECTURE TO REDUCE MEMORY BANDWIDTH BOTTLENECKS AND FACILITATE POWER MANAGEMENT

Abstract:

A system comprising a discrete graphics system-on-chip (SoC) to couple to a host processor unit, the SoC comprising a memory bridge comprising a first port to receive requests sent by a compute engine through a first path to the memory; and a second port to receive requests sent by a plurality of agents of the SoC through a second path to the memory.