Intel Corporation
Stacked transistor layout

Abstract:

An apparatus is provided which comprises: a first transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor body, a second transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, wherein the second transistor body is over the first dielectric layer and wherein the length of the second transistor body is non-parallel to the length of the first transistor body, and a gate coupled with the channel regions of both the first transistor body and the second transistor body. Other embodiments are also disclosed and claimed.