Intel Corporation
VERTICAL CHANNEL WITH CONDUCTIVE STRUCTURES TO IMPROVE STRING CURRENT

Abstract:

A vertical channel of a three-dimensional (3D) NAND has a recessed and filled drain/source pocket region for each memory cell to reduce resistance in a region that traditionally has high resistance. The vertical channel conducts current whose resistivity is controlled through a series of memory cells. The vertical channel can have a polysilicon material to conduct current past the memory cell gates and drain/sources region between the memory elements. The recess can extend the polysilicon away from a center of the vertical channel and closer to the control gates. The recess includes a structure to reduce resistance in the drain/source region along the vertical channel between memory cell gates.