Intel Corporation
TIER ARCHITECTURE FOR 3-DIMENSIONAL CROSS POINT MEMORY

Abstract:

A memory structure includes a plurality of memory cells between a first and a second terminal and a pair of first conductors within a first tier, where individual ones of the first conductors are coupled to the first terminal of a first adjacent pair of memory cells in a first row orthogonal to the first conductors. The memory structure further includes a pair of second conductors within a second tier and parallel to the first conductors, where individual ones of the second conductors are coupled to the first terminal of a second adjacent pair of memory cells in a second row. The memory structure further includes a third conductor between the first and second tiers, and between each of the pair of the first conductors and the pair of the second conductors. The third conductor is coupled to second terminals of both the first and second adjacent pairs of memory cells.