Intel Corporation
CORE STATUS MANAGEMENT AT POWER FAILURE

Abstract:

Embodiments herein relate to a power control unit (PCU) of an electronic device. The PCU may be configured to receive a power failure interrupt from an interrupt control block of the electronic device. The power failure interrupt may be generated based on or related to a power failure of the electronic device. In response to receipt of the power failure interrupt, and when a threshold number of processor cores related to the power failure is different than a number of awake processor cores of a set of processor cores of the electronic device, the PCU may transition a subset of processor cores of the set of processor cores to an awake state or a sleep state so that the number of awake processor cores is same as the threshold number of processor cores. Other embodiments may be described and/or claimed.